The generation of three-dimensional graphical images is of interest in a variety of electronic games and other applications. Computer graphics generally consists of instructions implemented via a graphics processing unit (GPU) executed on a computer system. The GPU can be envisioned as a pipeline through which pixel data pass. The data are used to define the image to be produced and displayed. The instructions are used to specify the calculations and operations needed to modify the data to produce rendered images that have a three-dimensional appearance.
In the initial stages of the pipeline, the desired image is composed using geometric shapes referred to as geometric primitives. In subsequent stages, effects such as texture, fog, and shading are added in order to enhance the realism of the image, and anti-aliasing and blending functions are also applied so that the rendered image will have a smoother and more realistic appearance. The results of the pipeline operations are stored in the frame buffer as pixels. The pixel values can be later read from the frame buffer and used to generate a display on a computer screen.
FIG. 1 illustrates one example of a conventional pipeline architecture, which is a “deep” pipeline having stages dedicated to performing specific functions. A transform stage 105 performs geometrical calculations of primitives and may also perform a clipping operation. A setup/raster stage 110 rasterizes the primitives. A texture address 115 stage and texture fetch 120 stage are utilized for texture mapping. A fog stage 130 implements a fog algorithm. An alpha test stage 135 performs an alpha test. A depth test 140 performs a depth test for culling occluded pixels. An alpha-blend stage 145 performs an alpha-blend color combination algorithm. A memory write stage 150 writes the output of the pipeline to memory.
There is an increasing interest in rendering three-dimensional graphical images in wireless phones, personal digital assistants (PDAs), and other devices where cost and power consumption are important design considerations. However, the conventional deep pipeline architecture requires a significant chip area, resulting in greater cost than desired. Additionally, a deep pipeline consumes significant power. As a result of cost and power considerations, the conventional deep pipeline architecture illustrated in FIG. 1 is considered unsuitable for wireless phones, PDAs and other such devices.